Variable-frequency pulse generator

ABSTRACT

The output (θ 2 ) of a digital adder ( 13 ) before being held by a first data holding circuit ( 14 ), a first reference value (D 1 ) and a second reference value (D 2 ) are compared, respectively, by a first data comparator ( 15 ) and a second data comparator ( 16 ), to thereby change one cycle of the output control of the pulse train fout from four cycles (T 1 -T 4 ) to two cycles (T 1 -T 2 ) of the reference clock. Further, by comparing the output (θ 1 ) of the first data holding circuit ( 14 ) and the first reference value (D 1 ) by a third data comparator ( 19 ), the latch timing of the overflow signal is changed from T 4  to T 1.

TECHNICAL FIELD

[0001] The present invention relates to a variable-frequency pulsegenerator capable of generating a pulse of the desired frequency.

BACKGROUND ART

[0002] A conventional variable-frequency pulse generator will beexplained below. A conventional variable-frequency pulse generator hasbeen disclosed in Japanese Patent Application No. 11-220364. FIG. 12shows a configuration of a variable-frequency pulse generator disclosedin the above publication.

[0003] In FIG. 12, the reference symbol 100 denotes a conventionalvariable-frequency pulse generation circuit, 101 denotes a bit inverterwhich inverts a first reference value D1, 102 denotes a data selectorwhich selects either one of the output of the inverter 101 and a pulsenumber set value Ps, 103 denotes a digital adder which adds the outputθ1 of a first data holding circuit described later and the output of thedata selector 102, and 104 denotes the first data holding circuit whichlatches the output θ2 of the digital adder 103 at the timing T2 of areference clock fb. The reference symbol 105 denotes a first datacomparator which compares the output θ1 of the first data holdingcircuit 104 and the first reference value D1, and 106 denotes a seconddata comparator which compares the output θ1 of the first data holdingcircuit 104 and a second reference value D2. The reference symbol 107denotes a pulse generation circuit which judges the output level (Highor Low) based on the two comparison results, 108 denotes a second dataholding circuit which latches the output fd of the pulse generationcircuit 107 at the timing T3 of the reference clock fb and outputs apulse train fout, and 109 denotes an overflow prevention circuit whichoutputs the overflow prevention signal fob synchronous with thereference clock fb based on the comparison result of the first datacomparator 105.

[0004] The control clock frequency fc is [fb/4]. The first referencevalue D1 is [fc×n], and the second reference value D2 is [(fc/2)×n]. Thepulse number set value per n seconds Ps is [Vp×n], and the value thereofcan be set for 1 unit in the range of [0≦Ps≦{ (fc/2)×n}]. n denotes themaximum cycle of the output pulse, and Vp denotes a speed set value.

[0005] The operation of the conventional variable-frequency pulsegenerator will now be explained. The inverter 101 outputs a bitinversion value of the reference value D1 in the 26-bit notation. Whenthe S terminal is 0 (θ1≦D1), the data selector 102 outputs the pulsenumber set value Ps (26-bit notation) of a terminal A to a terminal Y,and when the S terminal is 1 (θ1>D1), the data selector 102 outputs thebit inversion value of the reference value D1 of a terminal B to theterminal Y.

[0006] When a CIN terminal is 0 (θ1≦D1), the digital adder 103 adds thepulse number set value Ps output from the data selector 102 and theoutput θ1 of the first data holding circuit 104, and when the CINterminal is 1 (θ1>D1), the digital adder 103 adds −(fc×n), being the sumof the output of the data selector 102 and CIN=1, and the output θ1 ofthe first data holding circuit 104, and outputs the addition result θ2(26-bit notation) for each case. The first data holding circuit 104latches the addition result θ2 at the timing T2 of the reference clockfb and the overflow prevention signal fob, and out puts data θ1 (26-bitnotation).

[0007] The first data comparator 105 compares the output θ1 of the firstdata holding circuit 104 and the first reference value D1, and whenθ1>D1, outputs 1 as the overflow signal. The second data comparator 106compares the output θ1 of the first data holding circuit 104 and thesecond reference value D2. The pulse generation circuit 107 judges theboth comparison results, and for example, when the comparison results bythe both comparators are 0≦θ2<D2 (=(fc/2)×n), outputs 0 as the judgmentresult fd, and when D2≦θ<D1 (=fc×n), outputs 1, and when D1≦θ2, outputs0. The second data holding circuit 108 latches the judgment result fd atthe timing T3 of the reference clock fb, and outputs a pulse train fout.

[0008] The overflow prevention circuit 109 receives the overflow signaloutput from the first data comparator 105 at the timing T4 of thereference clock fb, and outputs an overflow prevention signal fob.

[0009]FIG. 13 is a timing chart which shows the operation of theconventional variable-frequency pulse generator. At first, the speedchange timing Δt changes at a period synchronous with the timing T1 ofthe reference clock fb and the speed change timing, and acceleration anddeceleration speed is latched at the timing T1 of the reference clockfb. This operation is executed by the part other than the configurationshown in FIG. 12.

[0010] The first data holding circuit 104 latches the output θ2 of thedigital adder 103 at the timing T2 of the reference clock fb. The seconddata holding circuit 108 then latches the output fd of the pulsegeneration circuit 107 at the timing T3 of the reference clock fb, andoutputs the pulse train fout.

[0011] The overflow prevention circuit 109 performs overflow preventionprocessing with respect to the output θ1 of the first data holdingcircuit 104, at the timing T4 of the reference clock fb. That is, whenoverflow occurs (θ1>D1), and fb=(High), the overflow prevention circuit109 outputs the overflow prevention signal fob (=High).

[0012] However, in the conventional variable-frequency pulse generator,control for four cycles of the reference clock is necessary during theperiod of from the speed setting until the overflow preventionprocessing is completed, that is, during 1 cycle of output control ofthe pulse train fout. Therefore, the reference clock of a frequency of 8times or more is required in order to actually obtain the pulse train ofa desired frequency (see FIG. 13). As a result, in the conventionalvariable-frequency pulse generator, with the speed-up of the referenceclock, there is caused a problem in that the noise, power consumptionand heat generation of the whole apparatus considerably increase.

[0013] It is an object of the present invention to provide avariable-frequency pulse generator capable of reducing the noise, powerconsumption and heat generation compared to the conventional apparatus.

DISCLOSURE OF THE INVENTION

[0014] The variable-frequency pulse generator according to the presentinvention has a configuration such that one cycle of output control ofthe pulse train is executed by two cycles of the reference clock, andfor example, comprises an inversion unit (corresponding to an inverter11 in the embodiment described later) which inverts a first referencevalue regulated by the reference clock, a selection unit (correspondingto a data selector 12) which selects the first reference value afterinversion, when an overflow has occurred, and in any other event selectsa predetermined value which changes depending on a set speed, a dataholding unit (corresponding to a first data holding circuit 14) whichlatches an output of a previous stage, being the present value of aresult of addition, in the second cycle of the reference clock and at apredetermined timing of an overflow prevention signal, an addition unit(corresponding to a digital adder 13) which adds the value selected bythe selection unit and the data latched by the data holding unit, afirst comparison unit (corresponding to a first data comparator 15)which compares the value obtained by the addition unit as a result ofaddition and the first reference value, a second comparison unit(corresponding to a second data comparator 16) which compares the valueobtained by the addition unit as a result of addition and a secondreference value which is half of the first reference value, a judgmentunit (corresponding to a pulse generation circuit 17) which judgeswhether a condition “0≦addition result<second reference value” issatisfied, or whether a condition “second reference value≦additionresult<first reference value” is satisfied, or whether a condition“first reference value≦addition result” is satisfied, and outputs aspecified signal corresponding to a result of the judgment, a pulsetrain output unit (corresponding to a second data holding circuit 18)which latches the specified signal at a predetermined timing of thesecond cycle of the reference clock, and outputs a pulse train of adesired frequency, a third comparison unit (corresponding to a thirddata comparator 19) which compares the data latched by the data holdingunit and the first reference value, and when a condition “latcheddata≧first reference value” is satisfied, judges that the overflow hasoccurred, and an overflow prevention unit (corresponding to an overflowprevention circuit 20) which outputs the overflow prevention signal at apredetermined timing of the first cycle of the reference clock, when thethird comparison unit has judged that the overflow has occurred.

[0015] The variable-frequency pulse generator according to the nextinvention has a configuration such that one cycle of output control ofthe pulse train is executed by two cycles of the reference clock, andfor example, comprises an addition unit (corresponding to a digitaladder 21) which adds a predetermined value, which changes depending on aset speed, and data latched at a predetermined timing of the secondcycle of the reference clock, a subtraction unit (corresponding to adigital subtracter 22) which subtracts a first reference value regulatedby the reference clock from the value obtained by the addition unit as aresult of addition, a first comparison unit (corresponding to a firstdata comparator 25) which compares the value obtained by the additionunit as a result of addition and the first reference value, and when acondition “addition result≧first reference value” is satisfied, judgesthat an overflow has occurred, a second comparison unit (correspondingto a second data comparator 26) which compares the value obtained by theaddition unit as a result of addition and a second reference value whichis half of the first reference value, a selection unit (corresponding toa data selector 23) which selects the value obtained by the subtractionunit as a result of subtraction when the overflow has occurred, and inany other event selects the value obtained by the addition unit as aresult of addition, a data holding unit (corresponding to a first dataholding circuit 24) which latches the value selected by the selectionunit at a predetermined timing of the second cycle of the referenceclock, a judgment unit (corresponding to a pulse generation circuit 27)which judges based on each the results of comparisons in the firstcomparison unit and the second comparison unit, whether a condition“0≦addition result<second reference value” is satisfied, or whether acondition “second reference value≦addition result<first reference value”is satisfied, or whether a condition “first reference value≦additionresult” is satisfied, and outputs a specified signal according to aresult of the judgment, and a pulse train output unit (corresponding toa second data holding circuit 28) which latches the specified signal ata predetermined timing of the second cycle of the reference clock, andoutputs a pulse train of a desired frequency.

[0016] The variable-frequency pulse generator according to the nextinvention has a configuration such that one cycle of output control ofthe pulse train is executed by two cycles of the reference clock, andfor example, comprises an inversion unit which inverts a reference valueregulated by the reference clock, a selection unit which selects thereference value after inversion, when an overflow has occurred, and inany other event selects a predetermined value which changes depending ona set speed, a data holding unit which latches an output of a previousstage, being the present value of a result of addition, in the secondcycle of the reference clock and at a predetermined timing of anoverflow prevention signal, an addition unit which adds the valueselected by the selection unit and the data latched by the data holdingunit, a first comparison unit which compares the value obtained by theaddition unit as a result of addition and the reference value, ajudgment unit (corresponding to a pulse generation circuit 17 c) whichjudges whether a condition “the overflow frequency is an even number”and “0≦addition result<reference value” is satisfied, or whether acondition “the over flow frequency is an even number” and “referencevalue≦addition result” is satisfied, or whether conditions “the overflowfrequency is an odd number” and “0≦addition result<reference value” aresatisfied, or whether conditions “the overflow frequency is an oddnumber” and “reference value≦addition result” are satisfied, and outputsa specified signal corresponding to a result of the judgment, a pulsetrain output unit which latches the specified signal at a predeterminedtiming of the second cycle of the reference clock, and outputs a pulsetrain of a desired frequency, a second comparison unit which comparesthe data latched by the data holding unit and the reference value, andwhen a condition “latched data≧reference value” is satisfied, judgesthat the overflow has occurred, and an overflow prevention unit whichoutputs the overflow prevention signal at a predetermined timing of thefirst cycle of the reference clock, when the second comparison unit hasjudged that the overflow has occurred.

[0017] The variable-frequency pulse generator according to the nextinvention has a configuration such that one cycle of output control ofthe pulse train is executed by two cycles of the reference clock, andfor example, comprises an inversion unit which inverts a first referencevalue regulated by the reference clock, a selection unit which selectsthe first reference value after inversion, when an overflow hasoccurred, and in any other event selects a predetermined value whichchanges depending on a set speed, a data holding unit which latches anoutput of a previous stage, being the present value of a result ofaddition, in the second cycle of the reference clock and at apredetermined timing of the overflow prevention signal, an addition unitwhich adds the value selected by the selection unit and the data latchedby the data holding unit, a first comparison unit which compares thevalue obtained by the addition unit as a result of addition and thefirst reference value, a second comparison unit which compares the valueobtained by the addition unit as a result of addition and a secondreference value which is half of the first reference value, a judgmentunit which judges whether a condition “0≦addition result<secondreference value” is satisfied, or whether a condition “second referencevalue≦addition result<first reference value” is satisfied, or whether acondition “first reference value≦addition result<(second referencevalue×3) “is satisfied, or whether a condition” (second referencevalue×3)≦addition result” is satisfied, and outputs a specified signalcorresponding to a result of the judgment, a pulse train output unitwhich latches the specified signal at a predetermined timing of thesecond cycle of the reference clock, and outputs a pulse train of adesired frequency, a third comparison unit (corresponding to a thirddata comparator 19 d) which compares the data latched by the dataholding unit and the first reference value, and when a condition“latched data>first reference value” is satisfied, judges that theoverflow has occurred, and an overflow prevention unit which outputs theoverflow prevention signal at a predetermined timing of the first cycleof the reference clock, when the third comparison unit has judged thatthe overflow has occurred.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018]FIG. 1 shows the configuration of a first embodiment of avariable-frequency pulse generator according to the present invention,

[0019]FIG. 2 is a timing chart which shows the operation of thevariable-frequency pulse generator in the first embodiment,

[0020]FIG. 3 shows the output result of each section, when thevariable-frequency pulse generator in the first embodiment is operated,

[0021]FIG. 4 shows the output waveform of the variable-frequency pulsegenerator in the first embodiment,

[0022]FIG. 5 shows the configuration of a second embodiment of thevariable-frequency pulse generator according to the present invention,

[0023]FIG. 6 is a timing chart which shows the operation of thevariable-frequency pulse generator in the second embodiment,

[0024]FIG. 7 shows the output result of each section, when thevariable-frequency pulse generator in the second embodiment is operated,

[0025]FIG. 8 shows the configuration of a third embodiment of thevariable-frequency pulse generator according to the present invention,

[0026]FIG. 9 shows the output result of each section, when thevariable-frequency pulse generator in the third embodiment is operated,

[0027]FIG. 10 shows the configuration of a fourth embodiment of thevariable-frequency pulse generator according to the present invention,

[0028]FIG. 11 shows the output result of each section, when thevariable-frequency pulse generator in the fourth embodiment is operated,

[0029]FIG. 12 shows the configuration of a conventionalvariable-frequency pulse generator, and

[0030]FIG. 13 is a timing chart which shows the operation of theconventional variable-frequency pulse generator.

BEST MODE FOR CARRYING OUT THE INVENTION

[0031] Embodiments of the variable-frequency pulse generator accordingto this invention will be explained in detail below with reference tothe accompanying drawings. However, this invention is not limited bythese embodiments.

First Embodiment

[0032]FIG. 1 shows the configuration of a first embodiment of thevariable-frequency pulse generator according to the present invention.In FIG. 1, the reference symbol 1 a denotes a variable-frequency pulsegeneration circuit in the first embodiment, 11 denotes a bit inverterwhich inverts a first reference value D1, 12 denotes a data selectorwhich selects either one of the output of the inverter 11 and a pulsenumber set value Ps, 13 denotes a digital adder which adds the output θ1of a first data holding circuit 14 described later and the output of thedata selector 12, and 14 denotes a first data holding circuit whichlatches the output θ2 of the digital adder 13 at the timing T2 of areference clock fb. The reference symbol 15 denotes a first datacomparator which compares the output θ2 of the digital adder 13 and thefirst reference value D1, and 16 denotes a second data comparator whichcompares the output θ2 of the digital adder 13 and a second referencevalue D2. The reference symbol 17 denotes a pulse generation circuitwhich judges the output level (High or Low) based on the two comparisonresults, 18 denotes a second data holding circuit which latches theoutput fd of the pulse generation circuit 17 at the timing T2 of thereference clock fb and outputs a pulse train fout, 19 denotes a thirddata comparator which compares the output θ1 of the first data holdingcircuit 14 and the first reference value D1, and 20 denotes an overflowprevention circuit which outputs an overflow prevention signal fob basedon the comparison result of the third data comparator 19.

[0033] In the first embodiment, the control clock frequency fc is [fb/2], and the first reference value D1 is [fc×n], and the second referencevalue D2 is [(fc/2)×n]. The pulse number set value per n seconds Ps is[Vp×n], and the value there of can be set per one unit in the range of[0≦Ps≦{(fc/2)×n}]. However, n denotes the maximum cycle of the outputpulse, and Vp denotes a speed set value.

[0034] In the first embodiment, as one example, explanation is given byassuming that the reference clock frequency fb is 32 MHz, and themaximum cycle n of the output pulse is 2 seconds. In this case, thecontrol clock frequency fc becomes fc=fb/2=32 MHz/2=16 MHz, the firstreference value D1 becomes D1=fc×n=16 MHz×2=32 M, the second referencevalue D2 becomes D2=(fc/2)×n=(16 MHz/2)×2=16 M, and the pulse number setvalue per n seconds (hereinafter referred to as a “pulse number setvalue”) Ps becomes 0≦Ps≦16 MHz. Therefore, the speed set value Vpbecomes 0≦Vp≦8 MHz.

[0035] The operation of the variable-frequency pulse generator in thefirst embodiment will now be explained. The inverter 11 outputs a bitinversion value of the reference value D1 in the 26-bit notation. Whenthe S terminal is 0 (θ1<D1), the data selector 12 outputs the pulsenumber set value Ps (26-bit notation) of a terminal A to a terminal Y,and when the S terminal is 1 (θ1≧D1), the data selector 12 outputs thebit inversion value of the reference value D1 of a terminal B to theterminal Y.

[0036] When the CIN terminal is 0 (θ1<D1), the digital adder 13 adds thepulse number set value Ps output from the data selector 12 and theoutput θ1 of the first data holding circuit 14, and when the CINterminal is 1 (θ1<D1), the digital adder 13 adds −(fc×n), being the sumof the output of the data selector 12 and CIN=1, and the output θ1 ofthe first data holding circuit 14, and outputs the addition result θ2(26-bit notation) for each case. The first data holding circuit 14latches the addition result θ2 at the timing T2 of the reference clockfb and the overflow prevention signal fob, and outputs data θ1 (26-bitnotation).

[0037] The first data comparator 15 compares the output θ2 of thedigital adder 13 and the first reference value D1. The second datacomparator 16 compares the output θ2 of the digital adder 13 and thesecond reference value D2. The pulse generation circuit 17 judges theboth comparison results, and for example, when the comparison results bythe both comparators are 0≦θ2<D2 (=(fc/2)×n), outputs 0 as the judgmentresult fd, and when D2≦θ2<D1 (=fc×n), outputs 1, and when D1≦θ2, outputs0. The second data holding circuit 18 latches the judgment result fd atthe timing T2 of the reference clock fb, and outputs a pulse train fout.

[0038] The third data comparator 19 compares the output θ1 of the firstdata holding circuit 14 and the first reference value D1, and whenθ1<D1, outputs 0, and when θ1≧D1, outputs 1. The overflow preventioncircuit 20 receives the output of the third data comparator 19 at thetiming T1 of the reference clock fb, and outputs an overflow preventionsignal fob.

[0039]FIG. 2 is a timing chart which shows the operation of thevariable-frequency pulse generator in the first embodiment. At first,the speed change timing Δt changes at a period synchronous with thetiming T1 of the reference clock fb and the speed change timing, andacceleration and deceleration speed is latched at the timing T1 of thereference clock fb. This operation is executed by the part other thanthe configuration shown in FIG. 1.

[0040] The first data holding circuit 14 latches the output θ2 of thedigital adder 103 at the timing T2 of the reference clock fb. The seconddata holding circuit 18 then latches the output fd of the pulsegeneration circuit 17, and outputs the pulse train fout.

[0041] The overflow prevention circuit 20 performs overflow preventionprocessing with respect to the output θ1 of the first data holdingcircuit 14, at the timing T1 of the reference clock fb. That is, whenoverflow occurs (θ1≧D1, and fb=High), the over flow prevention circuit20 outputs the overflow prevention signal fob (=High). In the firstembodiment, the above processing is repetitively executed at timings T1and T2 of the reference clock fb.

[0042]FIG. 3 shows the output result of each section, when thevariable-frequency pulse generator in the first embodiment is operated.Here, it is assumed that the reference clock fb is 32 MHz, the maximumcycle n of the output pulse is 2 seconds, and the pulse number set valuePs is 8→16 MHz (that is, the speed set value Vp is set to 4→8 MHz).Therefore, the control clock frequency fc becomes 16 MHz, the firstreference value D1 becomes 32 M, and the second reference value D2becomes 16 M.

[0043] In FIG. 3, for example, at the point of time when the elapsedtime is 0 second (initial state: 0/32 MHz), either of the pulse numberset value Ps (Vp×n), the output value θ1 of the first data holdingcircuit 14, the overflow signal, the output value θ2 of the digitaladder 13, the value fd, and the value fout is 0 (initial value).

[0044] When the elapsed time is 1/32 MHz (at the timing T1 of fb), thepulse number set value Ps is Vp×n=4 MHz×2=8 MHz, and the first dataholding circuit 14 holds the previous (elapsed time=0 second) outputvalue θ1 (=0). The third data comparator 19 outputs 0 (θ1<D1) as theoverflow signal. The output value θ2 of the digital adder 13 is θ2=θ1+Ps=0+8 MHz=8 MHz, since the overflow signal is 0. The output valuefd of the pulse generation circuit 17 is fd=0, since 0≦θ2<D2, and theoutput value fout of the second data holding circuit 18 holds theprevious fout value, and fout=0.

[0045] When the elapsed time is 2/32 MHz (at the timing T2 of fb), thepulse number set value Ps is Vp×n=8 MHz similar to the previous elapsedtime, and the first data holding circuit 14 latches the output value θ2immediately before (elapsed time=1/32 MHz) and the output value θ1thereof becomes θ1=8 MHz. The third data comparator 19 outputs 0 (θ1<D1)as the overflow signal. The output value θ2 of the digital adder 13 isθ2=θ1+Ps=8 MHz+8 MHz=16 MHz, since the overflow signal is 0. The outputvalue fd of the pulse generation circuit 17 is fd=1, since D2 ≦θ2<D1,and the second data holding circuit 18 latches the value fd (=0)immediately before and the output value fout thereof becomes fout=0.

[0046] When the elapsed time is 3/32 MHz (at the timing T1 of fb), thepulse number set value Ps is Vp×n=8 MHz similar to the previous elapsedtime, and the first data holding circuit 14 holds the previous (elapsedtime=2/32 MHz) output value θ1 (=8 MHz). The third data comparator 19outputs 0 (θ1<D1) as the overflow signal. The output value θ2 of thedigital adder 13 is θ2=θ1+Ps=8 MHz+8 MHz=16 MHz, since the overflowsignal is 0. The output value fd of the pulse generation circuit 17 isfd=1, since D2 ≦θ2<D1, and the second data holding circuit 18 holds theprevious value fout (=0) and the output value fout thereof becomesfout=0.

[0047] When the elapsed time is 4/32 MHz (at the timing T2 of fb), thepulse number set value Ps is Vp×n=8 MHz similar to the previous elapsedtime, and the first data holding circuit 14 latches the output value θ2immediately before (elapsed time=3/32 MHz) and the output value θ1thereof becomes θ1=16 MHz. The third data comparator 19 outputs 0(θ1<D1) as the overflow signal. The output value θ2 of the digital adder13 is θ2=θ1+Ps=16 MHz+8 MHz=24 MHz, since the overflow signal is 0. Theoutput value fd of the pulse generation circuit 17 is fd=1, sinceD2≦θ2≦D1, and the second data holding circuit 18 latches the value fd(=1) immediately before and the output value fout thereof becomesfout=1.

[0048] When the elapsed time is 5/32 MHz (at the timing T1 of fb), thepulse number set value Ps is Vp×n=8 MHz similar to the previous elapsedtime, and the first data holding circuit 14 holds the previous (elapsedtime=4/32 MHz) output value θ1 (=16 MHz). The third data comparator 19outputs 0 (θ1<D1) as the overflow signal. The output value θ2 of thedigital adder 13 is θ2=θ1+Ps=16 MHz+8 MHz=24 MHz, since the overflowsignal is 0. The output value fd of the pulse generation circuit 17 isfd=1, since D2≦θ2≦D1, and the second data holding circuit 18 holds theprevious value fout (=1) and the output value fout thereof becomesfout=1.

[0049] When the elapsed time is 6/32 MHz (at the timing T2 of fb), thepulse number set value Ps is Vp×n=8 MHz similar to the previous elapsedtime, and the first data holding circuit 14 latches the output value θ2immediately before (elapsed time=5/32 MHz) and the output value θ1thereof becomes θ1=24 MHz. The third data comparator 19 outputs 0(θ1<D1) as the overflow signal. The output value θ2 of the digital adder13 is θ2=θ1+Ps=24 MHz+8 MHz=32 MHz, since the overflow signal is 0. Theoutput value fd of the pulse generation circuit 17 is fd=0, since D1≦θ2,and the second data holding circuit 18 latches the value fd (=1)immediately before and the output value fout thereof becomes fout=1.

[0050] When the elapsed time is 7/32 MHz (at the timing T1 of fb), thepulse number set value Ps is Vp×n=8 MHz similar to the previous elapsedtime, and the first data holding circuit 14 holds the previous (elapsedtime=6/32MHz) output value θ1 (=24 MHz). The third data comparator 19outputs 0 (θ1<D1) as the overflow signal. The output value θ2 of thedigital adder 13 is θ2=θ1+Ps=24 MHz+8 MHz=32 MHz, since the overflowsignal is 0. The output value fd of the pulse generation circuit 17 isfd=0, since D2 ≦θ2, and the second data holding circuit 18 holds theprevious value fout (=1) and the output value fout thereof becomesfout=1.

[0051] When the elapsed time is 8/32 MHz (at the timing T2 of fb), thepulse number set value Ps is Vp×n=8 MHz similar to the previous elapsedtime, and the first data holding circuit 14 latches the output value θ2immediately before (elapsed time=7/32 MHz) and the output value θ1thereof becomes θ1=32 MHz. The third data comparator 19 outputs 1(θ1>D1) as the overflow signal. The output value θ2 of the digital adder13 is θ2=θ1−D1=32 MHz−32 MHz=0 MHz, since the overflow signal is 1. Theoutput value fd of the pulse generation circuit 17 is fd=0, since0≦θ2≦D2, and the second data holding circuit 18 latches the value fd(=0) immediately before and the output value fout thereof becomesfout=0.

[0052] When the elapsed time is 9/32 MHz (at the timing T1 of fb), thepulse number set value Ps is changed to Vp×n=16 MHz, and the first dataholding circuit 14 latches the output value θ2 immediately before(elapsed time=8/32 MHz), and the output value θ1 thereof becomes θ1=0MHz. The third data comparator 19 outputs 0 (θ1<D1) as the over flowsignal. The output value θ2 of the digital adder 13 is θ2=θ1+Ps=0 MHz+16MHz=16 MHz, since the overflow signal is 0. The output value fd of thepulse generation circuit 17 is fd=1, since D2≦θ2<D1, and the second dataholding circuit 18 holds the previous value fout (=0) and the outputvalue fout thereof becomes fout=0.

[0053] When the elapsed time is 10/32 MHz (at the timing T2 of fb), thepulse number set value Ps is Vp×n=16 MHz similar to the previous elapsedtime, and the first data holding circuit 14 latches the output value θ2immediately before (elapsed time=9/32 MHz) and the output value θ1thereof becomes θ1=16 MHz. The third data comparator 19 outputs 0(θ1<D1) as the overflow signal. The output value θ2 of the digital adder13 is θ2=θ1+Ps=16 MHz+16 MHz=32 MHz, since the overflow signal is 0. Theoutput value fd of the pulse generation circuit 17 is fd=1, sinceD2≦θ2<D1, and the second data holding circuit 18 latches the value fd(=1) immediately before and the output value fout thereof becomesfout=1.

[0054] Hereinafter, the similar operation is performed for the elapsedtime 11/32MHz and the elapsed time 12/32 MHz, . . . , and the output asshown in FIG. 3 can be obtained.

[0055]FIG. 4 shows the output waveform of the variable-frequency pulsegenerator in the first embodiment. In the variable-frequency pulsegenerator, during the elapsed time of from 0 to 8 [unit of 31.25 ns],that is, during 31.25×8=250 ns, the speed set value is Vp=4 MHz, and theoutput pulse fout becomes also 4 MHz, and it is seen that the pulse isoutput as per the speed set value Vp. On the other hand, during theelapsed time of from 8 to 16 [unit of 31.25 ns], that is, during31.25×8=250 ns, the speed set value is Vp=8 MHz, and the output pulsefout becomes also 8 MHz, and it is also seen that the pulse is output asper the speed set value Vp. In this manner, in the variable-frequencypulse generator in the first embodiment, the output pulse changescorresponding to the change in the speed set value.

[0056] As described above, in the first embodiment, one cycle of theoutput control of the pulse train fout is changed from four cycles(T1-T4) to two cycles (T1-T2) of the reference clock, by comparing theoutput θ2 of the digital adder 13 before being held by the first dataholding circuit 14, and the first reference value D1 and the secondreference value D2, respectively, by the first data comparator 15 andthe second data comparator 16. The latch timing of the over flow signalis also changed from T4 to T1 of the reference clock fb, by comparingthe output θ1 of the first data holding circuit 14 and the firstreference value D1 by the third data comparator 19. Thereby, the controlcycle can be reduced, and the noise, power consumption and heatgeneration can be reduced, compared to the conventional art.

Second Embodiment

[0057]FIG. 5 shows the configuration of a second embodiment of thevariable-frequency pulse generator according to the present invention.In FIG. 5, the reference symbol 1 b denotes a variable-frequency pulsegeneration circuit in the second embodiment, 21 denotes a digital adderwhich adds the output θ1 of a first data holding circuit 24 describedlater and the pulse number set value Ps, and 22 denotes a digitalsubtracter which subtracts a first reference value D1 from the output θ2of the digital adder 21. The reference symbol 23 denotes a data selectorwhich selects either one of the output of the output θ2 of the digitaladder 21 and the output θ3 of the digital subtracter 22, 24 denotes afirst data holding circuit which latches the output of the data selector23 at the timing T2 of the reference clock fb, 25 denotes a first datacomparator which compares the output θ2 of the digital adder 21 and thefirst reference value D1, and 26 denotes a second data comparator whichcompares the output θ2 of the digital adder 21 and the second referencevalue D2. The reference symbol 27 denotes a pulse generation circuitwhich judges the output level (High or Low) based on the two comparisonresults, and 28 denotes a second data holding circuit which latches theoutput fd of the pulse generation circuit 27 at the timing T2 of thereference clock fb and outputs a pulse train fout.

[0058] In the second embodiment, the control clock frequency fc is [fb/2]. The first reference value D1 is [fc×n], and the second referencevalue D2 is [(fc/2)×n]. The pulse number set value per n seconds Ps is[Vp×n], and the value thereof can be set per one unit in the range of[0≦Ps≦{(fc/2)×n}]. n denotes the maximum cycle of the output pulse, andVp denotes a speed set value.

[0059] In the second embodiment, as one example, explanation is given byassuming that the reference clock frequency fb is 32 MHz, and themaximum cycle n of the output pulse is 2 seconds. In this case, thecontrol clock frequency fc becomes fc=fb/2=32 MHz/2=16 MHz, the firstreference value D1 becomes D1=fc×n=16 MHz×2=32 M, the second referencevalue D2 becomes D2=(fc/2)×n=(16 MHz/2)×2=16 M, and the pulse number setvalue per n seconds (hereinafter referred to as a “pulse number setvalue”) Ps becomes 0≦Ps≦16 MHz. Therefore, the speed set value Vpbecomes 0≦Vp≦8 MHz.

[0060] The operation of the variable-frequency pulse generator in thesecond embodiment will now be explained. The digital adder 21 adds thepulse number set value Ps (26-bit notation) and the output θ1 of thefirst data holding circuit 24 (26-bit notation), and outputs theaddition result θ2 (26-bit notation) However, 0≦θ2<((fc/2)×n+fc×n) Thedigital subtracter 22 subtracts the first reference value D1 from theoutput θ2 of the digital adder 21, and outputs the subtraction result θ3(26-bit notation) However, −(fc×n)≦θ3<((fc/2)×n).

[0061] When the S terminal is 1−(θ2<D1), the data selector 23 outputsthe data θ2 of the terminal B to the terminal Y, and when the S terminalis 0 (θ2≧D1), the data selector 23 outputs the data θ3 of the terminal Ato the terminal Y. The first data holding circuit 24 latches the outputof the data selector 23 at the timing T2 of the reference clock fb, andoutputs data θ1 (26-bit notation) However, 0≦θ1<(fc×n).

[0062] The first data comparator 25 compares the output θ2 of thedigital adder 21 and the first reference value D1. The second datacomparator 26 compares the output θ2 of the digital adder 13 and thesecond reference value D2. The pulse generation circuit 27 judges theboth comparison results, and for example, when the comparison results bythe both comparators are 0≦θ2<D2 (=(fc/2)×n), outputs 0 as the judgmentresult fd, and when D2≦θ2<D1 (=fc ×n), outputs 1, and when D1≦θ2,outputs 0. The second data holding circuit 28 latches the judgmentresult fd at the timing T2 of the reference clock fb, and outputs apulse train fout.

[0063]FIG. 6 is a timing chart which shows the operation of thevariable-frequency pulse generator in the second embodiment. At first,the speed change timing Δt changes at a period synchronous with thetiming T1 of the reference clock fb and the speed change timing, andacceleration and deceleration speed is latched at the timing T1 of thereference clock fb. This operation is executed by the part other thanthe configuration shown in FIG. 5.

[0064] The first data holding circuit 24 latches the output of the dataselector 23 at the timing T2 of the reference clock fb. The second dataholding circuit 28 then latches the output fd of the pulse generationcircuit 27, and outputs the pulse train fout.

[0065]FIG. 7 shows the output result of each section, when thevariable-frequency pulse generator in the second embodiment is operated.Here, it is assumed that the reference clock fb is 32 MHz, the maximumcycle n of the output pulse is 2 seconds, and the pulse number set valuePs is 8→16 MHz (that is, the speed set value Vp is set to 4→8 MHz).Therefore, the control clock frequency fc becomes 16 MHz, the firstreference value D1 becomes 32 M, and the second reference value D2becomes 16 M.

[0066] In FIG. 7, for example, at the point of time when the elapsedtime is 0 second (initial state: 0/32 MHz), either of the pulse numberset value Ps (Vp×n), the output value θ1 of the first data holdingcircuit 24, the output value θ2 of the digital adder 21, the outputvalue θ3 of the digital subtracter 22, the value of Pin, the value fd,and the value fout is 0 (initial value).

[0067] When the elapsed time is 1/32 MHz (at the timing T1 of fb), thepulse number set value Ps is Vp×n=4 MHz×2=8 MHz, and the first dataholding circuit 24 holds the previous (elapsed time=0 second) outputvalue θ1 (=0). The output value θ2 of the digital adder 21 isθ2=θ1+Ps=0+8 MHz=8 MHz, and output value θ3 of the digital subtracter 22is θ3=θ2−D1=8 MHz−32 MHz=−24 MHz. At this time, the output Pin of thedata selector 23 becomes θ2. The output value fd of the pulse generationcircuit 27 is fd=0, since 0≦θ2<D2, and the output value fout of thesecond data holding circuit 28 holds the previous fout value, andfout=0.

[0068] When the elapsed time is 2/32 MHz (at the timing T2 of fb), thepulse number set value Ps is Vp×n=8 MHz similar to the previous elapsedtime, and the first data holding circuit 24 latches the output valuePin=θ2 immediately before (elapsed time=1/32 MHz) and the output valueθ1 there of becomes θ1=8 MHz. The output value θ2 of the digital adder21 is θ2=θ1+Ps=8 MHz+8 MHz=16 MHz, and the output value θ3 of thedigital subtracter 22 is θ3=θ2−D1=16 MHz−32 MHz=−16 MHz. At this time,the output Pin of the data selector 23 becomes θ2. The output value fdof the pulse generation circuit 27 is fd=1, since D2≦θ2<<D1, and thesecond data holding circuit 28 latches the value fd (=0) immediatelybefore and the output value fout thereof becomes fout=0.

[0069] When the elapsed time is 3/32 MHz (at the timing T1 of fb), thepulse number set value Ps is Vp×n=4 MHz×2=8 MHz, and the first dataholding circuit 24 holds the previous (elapsed time=2/32 MHz) outputvalue θ1 (=8 MHz) The output value θ2 of the digital adder 21 isθ2=θ1+Ps=8 MHz+8 MHz=16 MHz, and the output value θ3 of the digitalsubtracter 22 is θ3=θ2−D1=16 MHz−32 MHz=−16 MHz. At this time, theoutput Pin of the data selector 23 becomes θ2. The output value fd ofthe pulse generation circuit 27 is fd=1, since D2≦θ2<D1, and the seconddata holding circuit 28 holds the previous value fout and the outputvalue fout thereof becomes fout=0.

[0070] When the elapsed time is 4/32 MHz (at the timing T2 of fb), thepulse number set value Ps is Vp×n=8 MHz similar to the previous elapsedtime, and the first data holding circuit 24 latches the output valuePin=θ2 immediately before (elapsed time=3/32 MHz) and the output valueθ1 thereof becomes θ1=16 MHz. The output value θ2 of the digital adder21 is θ2=θ1+Ps=16 MHz+8 MHz=24 MHz, and the output value θ3 of thedigital subtracter 22 is θ3=θ2−D1=24 MHz−32 MHz−8 MHz. At this time, theoutput Pin of the data selector 23 becomes θ2. The output value fd ofthe pulse generation circuit 27 is fd=1, since D2≦θ2<D1, and the seconddata holding circuit 28 latches the value fd (=1) immediately before andthe output value fout thereof becomes fout=1.

[0071] When the elapsed time is 5/32 MHz (at the timing T1 of fb), thepulse number set value Ps is Vp×n=4 MHz×2=8 MHz, and the first dataholding circuit 24 holds the previous (elapsed time=4/32 MHz) outputvalue θ1 (=16 MHz). The output value θ2 of the digital adder 21 is θ2=θ1+Ps=16 MHz+8 MHz=24 MHz, and the output value θ3 of the digitalsubtracter 22 is θ3=θ2−D1=24 MHz−32 MHz=−8 MHz. At this time, the outputPin of the data selector 23 becomes θ2. The output value fd of the pulsegeneration circuit 27 is fd=1, since D2≦θ2<D1, and the second dataholding circuit 28 holds the previous value fout and the output valuefout thereof becomes fout=1.

[0072] When the elapsed time is 6/32 MHz (at the timing T2 of fb), thepulse number set value Ps is Vp×n=8 MHz similar to the previous elapsedtime, and the first data holding circuit 24 latches the output valuePin=θ2 immediately before (elapsed time=5/32 MHz) and the output valueθ1 thereof becomes θ1=24 MHz. The output value θ2 of the digital adder21 is θ2=θ1+Ps=24 MHz+8 MHz=32 MHz, and the output value θ3 of thedigital subtracter 22 is θ3=θ2−D1=32 MHz−32 MHz=0 MHz. At this time, theoutput Pin of the data selector 23 becomes θ3. The output value fd ofthe pulse generation circuit 27 is fd=0, since D1≦θ2, and the seconddata holding circuit 28 latches the value fd (=1) immediately before andthe output value fout thereof becomes fout=1.

[0073] When the elapsed time is 7/32 MHz (at the timing T1 of fb), thepulse number set value Ps is Vp×n=4 MHz×2=8 MHz, and the first dataholding circuit 24 holds the previous (elapsed time=6/32 MHz) outputvalue θ1 (=24 MHz). The output value θ2 of the digital adder 21 isθ2=θ1+Ps=24 MHz+8 MHz=32 MHz, and the output value θ3 of the digitalsubtracter 22 is θ3=θ2−D1=32 MHz−32 MHz=0 MHz. At this time, the outputPin of the data selector 23 becomes θ3. The output value fd of the pulsegeneration circuit 27 is fd=0, since D2≦θ2, and the second data holdingcircuit 28 holds the previous value fout and the output value foutthereof becomes fout=1.

[0074] When the elapsed time is 8/32 MHz (at the timing T2 of fb), thepulse number set value Ps is Vp×n=8 MHz similar to the previous elapsedtime, and the first data holding circuit 24 latches the output valuePin=θ3 immediately before (elapsed time=7/32 MHz) and the output valueθ1 there of becomes θ1=0 MHz. The output value θ2 of the digital adder21 is θ2=θ1+Ps=0 MHz+8 MHz=8 MHz, and the output value θ3 of the digitalsubtracter 22 is θ3=θ2−D1=8 MHz−32 MHz=−24 MHz. At this time, the outputPin of the data selector 23 becomes θ2. The output value fd of the pulsegeneration circuit 27 is fd=0, since 0≦θ2<D2, and the second dataholding circuit 28 latches the value fd (=0) immediately before and theoutput value fout thereof becomes fout=0.

[0075] When the elapsed time is 9/32 MHz (at the timing T1 of fb), thepulse number set value Ps is changed to Vp×n=16 MHz, and the first dataholding circuit 24 holds the previous (elapsed time=8/32 MHz) outputvalue θ1 (=0 MHz) The output value θ2 of the digital adder 21 isθ2=θ1+Ps=0 MHz+16 MHz=16 MHz, and the output value θ3 of the digitalsubtracter 22 is θ3=θ2−D1=16 MHz−32 MHz−−16 MHz. At this time, theoutput PiN of the data selector 23 becomes θ2. The output value fd ofthe pulse generation circuit 27 is fd=1, since D2≦θ2<D1, and the seconddata holding circuit 28 holds the previous value fout and the outputvalue fout thereof becomes fout=0.

[0076] When the elapsed time is 10/32 MHz (at the timing T2 of fb), thepulse number set value Ps is Vp×n=16 MHz similar to the previous elapsedtime, and the first data holding circuit 24 latches the output valuePin=θ2 immediately before (elapsed time=9/32 MHz) and the output valueθ1 thereof becomes θ1=16 MHz. The output value θ2 of the digital adder21 is θ2=θ1+Ps=16 MHz+16 MHz=32 MHz, and the output value θ3 of thedigital subtracter 22 is θ3=θ2−D1=32 MHz−32 MHz=0 MHz. At this time, theoutput Pin of the data selector 23 becomes θ3. The output value fd ofthe pulse generation circuit 27 is fd=0, since D1≦θ2, and the seconddata holding circuit 28 latches the value fd (=1) immediately before andthe output value fout thereof becomes fout=1.

[0077] Hereinafter, similar operation is performed for the elapsed time11/32 MHz and the elapsed time 12/32 MHz, . . . , and the output asshown in FIG. 7 can be obtained. The output waveform of thevariable-frequency pulse generator in the second embodiment changescorresponding to the change in the speed set value, as in FIG. 4explained above.

[0078] As described above, in the second embodiment, one cycle of theoutput control of the pulse train fout is changed from four cycles(T1-T4) to two cycles (T1-T2) of the reference clock, by comparing theoutput θ2 of the digital adder 21 before being held by the first dataholding circuit 24, and the first reference value D1 and the secondreference value D2, respectively, by the first data comparator 25 andthe second data comparator 26. The digital subtracter 22 furthersubtracts the first reference value D1 from the output θ2 of the digitaladder 21, and when the comparison result by the first data comparator 25satisfies θ2≧D1, the data selector 23 selects and outputs θ3, being thesubtraction result, to thereby prevent the overflow of the digital adder21. Thereby, the control cycle can be reduced, and the noise, powerconsumption and heat generation can be reduced, compared to theconventional art.

Third Embodiment

[0079]FIG. 8 shows the configuration of a third embodiment of thevariable-frequency pulse generator according to the present invention.The same configuration as that of the first embodiment described aboveis denoted by the same reference symbol, and the explanation thereof isomitted. Only the operation different from that of the first embodimentwill be explained herein.

[0080] In FIG. 8, the reference symbol 1 c is a variable-frequency pulsegeneration circuit in the third embodiment, and 17 c is a pulsegeneration circuit which judges the output level (High or Low) based onthe comparison result of the second data comparator 16. As in the firstembodiment, the control clock frequency fc is [fb/2 ], and the secondreference value D2 is [(fc/2)×n]. In the second embodiment, as oneexample, explanation is given by assuming that the reference clockfrequency fb is 32 MHz, and the maximum cycle n of the output pulse is 2seconds.

[0081] The operation of the variable-frequency pulse generator in thethird embodiment will be explained. The inverter 11 outputs a bitinversion value of the reference value D2 in the 25-bit notation. Whenthe S terminal is 0 (θ1<D1), the data selector 12 outputs the pulsenumber set value Ps (25-bit notation) of the terminal A to the terminalY, and when the S terminal is 1 (θ1≧D2), the data selector 12 outputsthe bit inversion value of the reference value D2 of the terminal B tothe terminal Y.

[0082] When the CIN terminal is 0 (θ1<D2), the digital adder 13 adds thepulse number set value Ps output from the data selector 12 and theoutput θ1 of the first data holding circuit 14, and when the CINterminal is 1 (θ1≧D2), the digital adder 13 adds −(fc/2×n), being thesum of the output of the data selector 12 and CIN=1, and the output θ1of the first data holding circuit 14, and outputs the addition result θ2(25-bit notation) for each case. The first data holding circuit 14latches the addition result θ2 at the timing T2 of the reference clockfb and the overflow prevention signal fob, and outputs data θ1 (25-bitnotation)

[0083] The second data comparator 16 compares the output θ2 of thedigital adder 13 and the second reference value D2. The pulse generationcircuit 17 c judges the comparison result of the second data comparator16, and for example, when the comparison result is 0≦θ2<D2 (=(fc/2)×n)and the overflow is even number of times, outputs 0 as the judgmentresult fd, and when D2≦θ2 and the overflow is even number of times,outputs 1, and when 0≦θ2<D2 (=(fc/2)×n) and the overflow is odd numberof times, outputs 1, and when D2≦θ2 and the overflow is odd number oftimes, outputs 0. The second data holding circuit 18 latches thejudgment result fd at the timing T2 of the reference clock fb, andoutputs a pulse train fout.

[0084] The third data comparator 19 compares the output θ1 of the firstdata holding circuit 14 and the second reference value D2, and whenθ1<D2, outputs 0, and when θ1≧D2, outputs 1. The overflow preventioncircuit 20 receives the output of the third data comparator 19 at thetiming T1 of the reference clock fb, and outputs an overflow preventionsignal fob.

[0085] The latch timing of the variable-frequency pulse generator in thethird embodiment is the same as that shown in FIG. 2 explained above,and hence the explanation thereof is omitted.

[0086]FIG. 9 shows the output result of each section, when thevariable-frequency pulse generator in the third embodiment is operated.It is assumed that the reference clock fb is 32 MHz, the maximum cycle nof the output pulse is 2 seconds, and the pulse number set value Ps is8→16 MHz (that is, the speed set value Vp is set to 4→8 MHz). Therefore,the control clock frequency fc becomes 16 MHz, and the second referencevalue D2 becomes 16 M.

[0087] In FIG. 9, for example, at the point of time when the elapsedtime is 0 second (initial state: 0/32 MHz), either of the pulse numberset value Ps (Vp×n), the output value θ1 of the first data holdingcircuit 14, the overflow signal, the output value θ2 of the digitaladder 13, the value fd, and the value fout is 0 (initial value).

[0088] When the elapsed time is 1/32 MHz (at the timing T1 of fb), thepulse number set value Ps is Vp×n=4 MHz×2=8 MHz, and the first dataholding circuit 14 holds the previous (elapsed time=0 second) outputvalue θ1 (=0). The third data comparator 19 outputs 0 (θ1<D2) as theoverflow signal. The output value θ2 of the digital adder 13 isθ2=θ1+Ps=0+8 MHz=8 MHz, since the overflow signal is 0. The output valuefd of the pulse generation circuit 17 c is fd=0, since the overflowfrequency is 0 (0 is designated as an even number) 0≦θ2<D2, and theoutput value fout of the second data holding circuit 18 holds theprevious fout value, and fout=0.

[0089] When the elapsed time is 2/32 MHz (at the timing T2 of fb), thepulse number set value Ps is Vp×n=8 MHz similar to the previous elapsedtime, and the first data holding circuit 14 latches the output value θ2immediately before (elapsed time=1/32 MHz) and the output value θ1thereof becomes θ1=8 MHz. The third data comparator 19 outputs 0 (θ1<D2)as the overflow signal. The output value θ2 of the digital adder 13 isθ2=θ1+Ps=8 MHz+8 MHz=16 MHz, since the overflow signal is 0. The outputvalue fd of the pulse generation circuit 17 c is fd=1, since theoverflow frequency is 0 and D2≦θ2, and the second data holding circuit18 latches the value fd (=0) immediately before and the output valuefout thereof becomes fout=0.

[0090] When the elapsed time is 3/32 MHz (at the timing T1 of fb), thepulse number set value Ps is Vp×n=8 MHz similar to the previous elapsedtime, and the first data holding circuit 14 holds the previous (elapsedtime=2/32 MHz) output value θ1 (=8 MHz). The third data comparator 19outputs 0 (θ1<D2) as the overflow signal. The output value θ2 of thedigital adder 13 is θ2=θ1+Ps=8 MHz+8 MHz=16 MHz, since the overflowsignal is 0. The output value fd of the pulse generation circuit 17 c isfd=1, since the overflow frequency is 0 and D2≦θ2, and the second dataholding circuit 18 holds the previous value fout (=0) and the outputvalue fout thereof becomes fout=0.

[0091] When the elapsed time is 4/32 MHz (at the timing T2 of fb), thepulse number set value Ps is Vp×n=8 MHz similar to the previous elapsedtime, and the first data holding circuit 14 latches the output value θ2immediately before (elapsed time=3/32 MHz) and the output value θ1thereof becomes θ1=16 MHz. The third data comparator 19 outputs 1(θ1≧D2) as the overflow signal. The output value θ2 of the digital adder13 is θ2=θ1−D2=16 MHz−16 MHz=0 MHz, since the overflow signal is 1. Theoutput value fd of the pulse generation circuit 17 c is fd=1, since theoverflow frequency is 1 and 0≦θ2<D2, and the second data holding circuit18 latches the value fd (=1) immediately before and the output valuefout thereof becomes fout=1.

[0092] When the elapsed time is 5/32 MHz (at the timing T1 of fb), thepulse number set value Ps is Vp×n=8 MHz similar to the previous elapsedtime, and the first data holding circuit 14 latches the output value θ2immediately before (elapsed time=4/32 MHz) and the output value θ1thereof becomes θ1=0 MHz. The third data comparator 19 outputs 0 (θ1<D2)as the overflow signal. The output value θ2 of the digital adder 13 isθ2=θ1+Ps=0 MHz+8 MHz=8 MHz, since the overflow signal is 0. The outputvalue fd of the pulse generation circuit 17 c is fd=1, since theoverflow frequency is 1 and 0≦θ2<D2, and the second data holding circuit18 holds the previous value fout (=1) and the output value fout thereofbecomes fout=1.

[0093] When the elapsed time is 6/32 MHz (at the timing T2 of fb), thepulse number set value Ps is Vp×n=8 MHz similar to the previous elapsedtime, and the first data holding circuit 14 latches the output value θ2immediately before (elapsed time=5/32 MHz) and the output value θ1thereof becomes θ1=8 MHz. The third data comparator 19 outputs 0 (θ1<D2)as the overflow signal. The output value θ2 of the digital adder 13 isθ2=θ1+Ps=8 MHz+8 MHz=16 MHz, since the overflow signal is 0. The outputvalue fd of the pulse generation circuit 17 c is fd=0, since theoverflow frequency is 1 and D2<θ2, and the second data holding circuit18 latches the value fd (=1) immediately before and the output valuefout thereof becomes fout=1.

[0094] When the elapsed time is 7/32 MHz (at the timing T1 of fb), thepulse number set value Ps is Vp×n=8 MHz similar to the previous elapsedtime, and the first data holding circuit 14 holds the previous (elapsedtime=6/32 MHz) output value θ1 (=8 MHz). The third data comparator 19outputs 0 (θ1<D2) as the overflow signal. The output value θ2 of thedigital adder 13 is θ2=θ1+Ps=8 MHz+8 MHz=16 MHz, since the overflowsignal is 0. The output value fd of the pulse generation circuit 17 c isfd=0, since the overflow frequency is 1 and D2≦θ2, and the second dataholding circuit 18 holds the previous value fout (=1) and the outputvalue fout thereof becomes fout=1.

[0095] When the elapsed time is 8/32 MHz (at the timing T2 of fb), thepulse number set value Ps is Vp×n=8 MHz similar to the previous elapsedtime, and the first data holding circuit 14 latches the output value θ2immediately before (elapsed time=7/32 MHz) and the output value θ1thereof becomes θ1 16 MHz. The third data comparator 19 outputs 1(θ1≧D2) as the overflow signal. The output value θ2 of the digital adder13 is θ2=θ1−D2=16 MHz−16 MHz=0 MHz, since the overflow signal is 1. Theoutput value fd of the pulse generation circuit 17 c is fd=0, since theoverflow frequency is 2 and 0≦θ2<D2, and the second data holding circuit18 latches the value fd (=0) immediately before and the output valuefout thereof becomes fout=0.

[0096] When the elapsed time is 9/32 MHz (at the timing T1 of fb), thepulse number set value Ps is changed to Vp×n=16 MHz, and the first dataholding circuit 14 latches the output value θ2 immediately before(elapsed time=8/32 MHz) and the output value θ1 becomes θ1=0 MHz. Thethird data comparator 19 outputs 0 (θ1<D2) as the overflow signal. Theoutput value θ2 of the digital adder 13 is θ2=θ1+Ps=0 MHz+16 MHz=16 MHz,since the overflow signal is 0. The output value fd of the pulsegeneration circuit 17 c is fd=1, since the overflow frequency is 2 andD2≦θ2, and the second data holding circuit 18 holds the previous valuefout (=0) and the output value fout thereof becomes fout=0.

[0097] When the elapsed time is 10/32 MHz (at the timing T2 of fb), thepulse number set value Ps is Vp×n=16 MHz similar to the previous elapsedtime, and the first data holding circuit 14 latches the output value θ2immediately before (elapsed time=9/32 MHz) and the output value θ1thereof becomes θ1=16 MHz. The third data comparator 19 outputs 1(θ1≧D2) as the overflow signal. The output value θ2 of the digital adder13 is θ2=θ1−D2=16 MHz−16 MHz=0 MHz, since the overflow signal is 1. Theoutput value fd of the pulse generation circuit 17 c is fd=1, since theoverflow frequency is 3 and 0≦θ2<D1, and the second data holding circuit18 latches the value fd (=1) immediately before and the output valuefout thereof becomes fout=1.

[0098] Hereinafter, similar operation is performed for the elapsed time11/32 MHz and the elapsed time 12/32 MHz, . . . , and the output asshown in FIG. 9 can be obtained. The output waveform of thevariable-frequency pulse generator in the third embodiment changescorresponding to the change in the speed set value, as in FIG. 4explained above.

[0099] As described above, in the third embodiment, one cycle of theoutput control of the pulse train fout is changed from four cycles(T1-T4) to two cycles (T1-T2) of the reference clock, by comparing theoutput θ2 of the digital adder 13 before being held by the first dataholding circuit 14, and the second reference value D2, respectively, bythe second data comparator 16. The latch timing of the overflow signalis also changed from T4 to T1 of the reference clock fb, by comparingthe output θ1 of the first data holding circuit 14 and the secondreference value D2 by the third data comparator 19. Thereby, the controlcycle can be reduced, and the noise, power consumption and heatgeneration can be reduced, compared to the conventional art.

[0100] Also, in the third embodiment, it is judged whether the overflowfrequency is an even number of times or an odd number of times, and thepulses are generated based on the judgment result and the comparisonresult by the second data comparator 16. Thereby, the number of gatescan be reduced than that in the first embodiment.

Fourth Embodiment

[0101]FIG. 10 shows the configuration of a fourth embodiment of thevariable-frequency pulse generator according to the present invention.The same configuration as that of the first embodiment described aboveis denoted by the same reference symbol, and the explanation thereof isomitted. Only the operation different from that of the first embodimentwill be explained herein.

[0102] In FIG. 10, the reference symbol 1 d is a variable-frequencypulse generation circuit in the third embodiment, and 17 d is a pulsegeneration circuit which judges the output level (High or Low) based onthe comparison result of the two data comparators, and 19 d is a thirddata comparator which compares the output θ1 of the first data holdingcircuit 14 and the first reference value D1. In the embodiment, as oneexample, explanation is given by assuming that the reference clockfrequency fb is 32 MHz, and the maximum cycle n of the output pulse is 2seconds.

[0103] The operation of the variable-frequency pulse generator in thefourth embodiment will be explained. When the S terminal is 0 (θ1≦D1),the data selector 12 outputs the pulse number set value Ps (26-bitnotation) of the terminal A to the terminal Y, and when the S terminalis 1 (θ1>D1), the data selector 12 outputs the bit inversion value ofthe reference value D1 of the terminal B to the terminal Y.

[0104] When the CIN terminal is 0 (θ1≦D1), the digital adder 13 adds thepulse number set value Ps output from the data selector 12 and theoutput θ1 of the first data holding circuit 14, and when the CINterminal is 1 (θ1>D1), the digital adder 13 adds −(fc×n), being the sumof the output of the data selector 12 and CIN=1, and the output θ1 ofthe first data holding circuit 14, and outputs the addition result θ2(26-bit notation) for each case.

[0105] The pulse generation circuit 17 d judges the comparison resultsof the first and second data comparators, and for example, when thecomparison results by the both comparators are 0≦θ2<D2 (=(fc/2)×n),outputs 0 as the judgment result fd, and when D2≦θ2<D1 (=fc×n), outputs1, and when D1≦θ2<(D2×3), outputs 0, and when (D2×3)≦θ2, outputs 1.

[0106] The third data comparator 19 d compares the output θ1 of thefirst data holding circuit 14 and the first reference value D1, and whenθ1≦D1, outputs 0, and when θ1>D1, outputs 1.

[0107] The latch timing of the variable-frequency pulse generator in thefourth embodiment is the same as that shown in FIG. 2 explained above,and hence the explanation thereof is omitted.

[0108]FIG. 11 shows the output result of each section, when thevariable-frequency pulse generator in the fourth embodiment is operated.It is assumed herein that the reference clock fb is 32 MHz, the maximumcycle n of the output pulse is 2 seconds, and the pulse number set valuePs is 8→16 MHz (that is, the speed set value Vp is set to 4→8 MHz).Therefore, the control clock frequency fc becomes 16 MHz, and the firstreference value D1 becomes 32 MHz, and the second reference value D2becomes 16 MHz.

[0109] In FIG. 11, for example, at the point of time when the elapsedtime is 0 second (initial state: 0/32 MHz), either of the pulse numberset value Ps (Vp×n), the output value θ1 of the first data holdingcircuit 14, the overflow signal, the output value θ2 of the digitaladder 13, the value fd, and the value fout is 0 (initial value).

[0110] When the elapsed time is 1/32 MHz (at the timing T1 of fb), thepulse number set value Ps is Vp×n=4 MHz×2=8 MHz, and the first dataholding circuit 14 holds the previous (elapsed time=0 second) outputvalue θ1 (=0). The third data comparator 19 d outputs 0 (θ1≦D1) as theoverflow signal. The output value θ2 of the digital adder 13 isθ2=θ1+Ps=0+8 MHz=8 MHz, since the overflow signal is 0. The output valuefd of the pulse generation circuit 17 d is fd=0, since 0≦θ2<D2, and theoutput value tout of the second data holding circuit 18 holds theprevious fout value, and tout=0.

[0111] When the elapsed time is 2/32 MHz (at the timing T2 of fb), thepulse number set value Ps is Vp×n=8 MHz similar to the previous elapsedtime, and the first data holding circuit 14 latches the output value θ2immediately before (elapsed time=1/32 MHz) and the output-value θ1thereof becomes θ1=8 MHz. The third data comparator 19 d outputs 0(θ1≦D1) as the overflow signal. The output value θ2 of the digital adder13 is θ2=θ1+Ps=8 MHz+8 MHz=16 MHz, since the overflow signal is 0. Theoutput value fd of the pulse generation circuit 17 d is fd=1, sinceD2≦θ2<D1, and the second data holding circuit 18 latches the value fd(=0) immediately before and the output value fout thereof becomesfout=0.

[0112] When the elapsed time is 3/32 MHz (at the timing T1 of fb), thepulse number set value Ps is Vp×n=8 MHz similar to the previous elapsedtime, and the first data holding circuit 14 holds the previous (elapsedtime=2/32 MHz) output value θ1 (=8 MHz). The third data comparator 19 doutputs 0 (θ1≦D1) as the overflow signal. The output value θ2 of thedigital adder 13 is θ2=θ1+Ps=8 MHz+8 MHz 16 MHz, since the overflowsignal is 0. The output value fd of the pulse generation circuit 17 d isfd=1, since D2≦θ2≦D1, and the second data holding circuit 18 holds theprevious value fout (=0) and the output value fout thereof becomesfout=0.

[0113] When the elapsed time is 4/32 MHz (at the timing T2 of fb), thepulse number set value Ps is Vp×n=8 MHz similar to the previous elapsedtime, and the first data holding circuit 14 latches the output value θ2immediately before (elapsed time=3/32 MHz) and the output value θ1thereof becomes θ1=16 MHz. The third data comparator 19 d outputs 0(θ1≦D1) as the overflow signal. The output value θ2 of the digital adder13 is θ2=θ1+Ps=16 MHz+8 MHz=24 MHz, since the overflow signal is 0. Theoutput value fd of the pulse generation circuit 17 d is fd=1, sinceD2≦θ2≦D1, and the second data holding circuit 18 latches the value fd(=1) immediately before and the output value fout thereof becomesfout=1.

[0114] When the elapsed time is 5/32 MHz (at the timing T1 of fb), thepulse number set value Ps is Vp×n=8 MHz similar to the previous elapsedtime, and the first data holding circuit 14 holds the previous (elapsedtime=4/32MHz) output value θ1 (=16 MHz). The third data comparator 19 doutputs 0 (θ1≦D1) as the overflow signal. The output value θ2 of thedigital adder 13 is θ2=θ1+Ps=16 MHz+8 MHz−24 MHz, since the overflowsignal is 0. The output value fd of the pulse generation circuit 17 d isfd=1, since D2 ≦θ2≦D1, and the second data holding circuit 18 holds theprevious value fout (=1) and the output value tout thereof becomesfout=1.

[0115] When the elapsed time is 6/32 MHz (at the timing T2 of fb), thepulse number set value Ps is Vp×n=8 MHz similar to the previous elapsedtime, and the first data holding circuit 14 latches the output value θ2immediately before (elapsed time=5/32 MHz) and the output value θ1thereof becomes θ1=24 MHz. The third data comparator 19 d outputs 0(θ1≦D1) as the overflow signal. The output value θ2 of the digital adder13 is θ2=θ1+Ps=24 MHz+8 MHz =32 MHz, since the overflow signal is 0. Theoutput value fd of the pulse generation circuit 17 d is fd=0, since D1≦θ2<(D2×3), and the second data holding circuit 18 latches the value fd(=1) immediately before and the output value fout thereof becomesfout=1.

[0116] When the elapsed time is 7/32 MHz (at the timing T1 of fb), thepulse number set value Ps is Vp×n=8 MHz similar to the previous elapsedtime, and the first data holding circuit 14 holds the previous (elapsedtime=6/32MHz) output value θ1 (=24 MHz). The third data comparator 19 doutputs 0 (θ1≦D1) as the overflow signal. The output value θ2 of thedigital adder 13 is θ2=θ1+Ps=24 MHz+8 MHz=32 MHz, since the overflowsignal is 0. The output value fd of the pulse generation circuit 17 d isfd=0, since D1 ≦θ2<(D2×3), and the second data holding circuit 18 holdsthe previous value fout (=1) and the out put value fout thereof becomesfout=1.

[0117] When the elapsed time is 8/32 MHz (at the timing T2 of fb), thepulse number set value Ps is Vp×n=8 MHz similar to the previous elapsedtime, and the first data holding circuit 14 latches the output value θ2immediately before (elapsed time=7/32 MHz) and the output value θ1thereof becomes θ1=32 MHz. The third data comparator 19 d outputs 0(θ1≦D1) as the overflow signal. The output value θ2 of the digital adder13 is θ2=θ1+Ps=32 MHz+8 MHz=40 MHz, since the overflow signal is 1. Theoutput value fd of the pulse generation circuit 17 d is fd=0, since D1≦θ2<(D2×3), and the second data holding circuit 18 latches the value fd(=0) immediately before and the output value fout thereof becomesfout=0.

[0118] When the elapsed time is 9/32 MHz (at the timing T1 of fb), thepulse number set value Ps is changed to Vp×n=16 MHz, and the first dataholding circuit 14 holds the previous (elapsed time=8/32 MHz) outputvalue θ1 (=32 MHz). The third data comparator 19 d outputs 0 (θ1 ≦D1) asthe overflow signal. The output value θ2 of the digital adder 13 isθ2=θ1+Ps=32 MHz+16 MHz=48 MHz, since the overflow signal is 0. Theoutput value fd of the pulse generation circuit 17 d is fd=1, since(D2×3)≦θ2, and the second data holding circuit 18 holds the previousvalue fout (=0) and the output value fout thereof becomes fout=0.

[0119] When the elapsed time is 10/32 MHz (at the timing T2 of fb), thepulse number set value Ps is Vp×n=16 MHz similar to the previous elapsedtime, and the first data holding circuit 14 latches the output value θ2immediately before (elapsed time=9/32 MHz) and the output value θ1thereof becomes θ1=48 MHz. The third data comparator 19 d outputs 1(θ1>D1) as the overflow signal. The output value θ2 of the digital adder13 is θ2=θ1−D1=48 MHz−32 MHz=16 MHz, since the overflow signal is 1. Theoutput value fd of the pulse generation circuit 17 d is fd=1, since D2≦θ2≦D1, and the second data holding circuit 18 latches the value fd (=1)immediately before and the output value fout thereof becomes fout=1 .

[0120] Hereinafter, similar operation is performed for the elapsed time11/32 MHz and the elapsed time 12/32 MHz, . . . , and the output asshown in FIG. 11 can be obtained. The output waveform of thevariable-frequency pulse generator in the fourth embodiment changescorresponding to the change in the speed set value, as in FIG. 4explained above.

[0121] As described above, in the fourth embodiment, one cycle of theoutput control of the pulse train fout is changed from four cycles(T1-T4) to two cycles (T1-T2) of the reference clock, by comparing theoutput θ2 of the digital adder 13 before being held by the first dataholding circuit 14, the first reference value D1 and the secondreference value D2, respectively, by the first data comparator 15 andthe second data comparator 16. The latch timing of the over flow signalis also changed from T4 to T1 of the reference clock fb. Thereby, thecontrol cycle can be reduced, and the noise, power consumption and heatgeneration can be reduced, compared to the conventional art.

[0122] As described above, according to the present invention, theoutput of the addition unit before being held by the data holding unit,the first reference value and the second reference value are compared,respectively, by the first comparison unit and the second comparisonunit, to thereby change one cycle of the output control of the pulsetrain from four cycles (T1-T4) to two cycles (T1-T2) of the referenceclock. Further, by comparing the output of the data holding unit and thefirst reference value by the third comparison unit, the latch timing ofthe overflow signal is changed from the fourth cycle (T4) to the firstcycle (T1). Thereby, the control cycle can be reduced, and hence thereis the effect that the noise, power consumption and heat generation canbe reduced, compared to the conventional art.

[0123] According to the next invention, the output of the addition unitbefore being held by the data holding unit, the first reference valueand the second reference value are compared, respectively, by the firstcomparison unit and the second comparison unit, to thereby change onecycle of the output control of the pulse train from four cycles (T1-T4)to two cycles (T1-T2) of the reference clock. Further, when thesubtraction unit subtracts the first reference value from the outputvalue of the addition unit, and the comparison result by the firstcomparison unit satisfies “addition result≧first reference value”, theselection unit prevents the overflow of the addition unit byselecting/outputting the subtraction result. Thereby, the control cyclecan be reduced, and hence there is the effect that the noise, powerconsumption and heat generation can be reduced, compared to theconventional art.

[0124] According to the next invention, it is judged whether theoverflow frequency is even number of times or odd number of times, andthe pulses are generated based on the judgment result and the comparisonresult by the second comparison unit. Thereby, there is the effect thatthe number of gates can be considerably reduced.

[0125] According to the next invention, the output of the addition unitbefore being held by the data holding unit, the first reference valueand the second reference value are compared, respectively, by the firstcomparison unit and the second comparison unit, to thereby change onecycle of the output control of the pulse train from four cycles (T1-T4)to two cycles (T1-T2) of the reference clock. Further, by comparing theoutput of the data holding unit and the first reference value by thethird comparison unit, the latch timing of the overflow signal ischanged from the fourth cycle (T4) to the first cycle (T1). Thereby, thecontrol cycle can be reduced, and hence there is the effect that thenoise, power consumption and heat generation can be reduced, compared tothe conventional art.

Industrial Applicability

[0126] As described above, the variable-frequency pulse generatoraccording to the present invention is useful for a variable-frequencypulse generator which generates a pulse train of a desired frequency,and particularly useful for all apparatus which uses avariable-frequency pulse generator in which the noise, power consumptionand heat generation within the apparatus considerably increase due tospeed-up of the reference block.

1. A variable-frequency pulse generator which executes one cycle ofoutput control of the pulse train by two cycles of a reference clock,comprising: an inversion unit which inverts a first reference valueregulated by the reference clock; a selection unit which selects thefirst reference value after inversion, when an overflow has occurred,and in any other event selects a predetermined value which changesdepending on a set speed; a data holding unit which latches an output ofa previous stage, being the present value of a result of addition, inthe second cycle of the reference clock and at a predetermined timing ofan overflow prevention signal; an addition unit which adds the valueselected by the selection unit and the data latched by the data holdingunit; a first comparison unit which compares the value obtained by theaddition unit as a result of addition and the first reference value; asecond comparison unit which compares the value obtained by the additionunit as a result of addition and a second reference value which is halfof the first reference value; a judgment unit which judges whether acondition “0<addition result≦second reference value” is satisfied, orwhether a condition “second reference value≦addition result<firstreference value” is satisfied, or whether a condition “first referencevalue≦addition result” is satisfied, and outputs a specified signalcorresponding to a result of the judgment; a pulse train output unitwhich latches the specified signal at a predetermined timing of thesecond cycle of the reference clock, and outputs a pulse train of adesired frequency; a third comparison unit which compares the datalatched by the data holding unit and the first reference value, and whena condition “latched data>first reference value” is satisfied, judgesthat the overflow has occurred; and an overflow prevention unit whichoutputs the overflow prevention signal at a predetermined timing of thefirst cycle of the reference clock, when the third comparison unit hasjudged that the overflow has occurred.
 2. A variable-frequency pulsegenerator which executes one cycle of output control of the pulse trainby two cycles of a reference clock, comprising: an addition unit whichadds a predetermined value, which changes depending on a set speed, anddata latched at a predetermined timing of the second cycle of thereference clock; a subtraction unit which subtracts a first referencevalue regulated by the reference clock from the value obtained by theaddition unit as a result of addition; a first comparison unit whichcompares the value obtained by the addition unit as a result of additionand the first reference value, and when a condition “additionresult≧first reference value” is satisfied, judges that an overflow hasoccurred; a second comparison unit which compares the value obtained bythe addition unit as a result of addition and a second reference valuewhich is half of the first reference value; a selection unit whichselects the value obtained by the subtraction unit as a result ofsubtraction when the overflow has occurred, and in any other eventselects the value obtained by the addition unit as a result of addition;a data holding unit which latches the value selected by the selectionunit at a predetermined timing of the second cycle of the referenceclock; a judgment unit which judges based on each the results ofcomparisons in the first comparison unit and the second comparison unit,whether a condition “0≦addition result<second reference value” issatisfied, or whether a condition “second reference value≦additionresult≦first reference value” is satisfied, or whether a condition“first reference value≦addition result” is satisfied, and outputs aspecified signal according to a result of the judgment; and a pulsetrain output unit which latches the specified signal at a predeterminedtiming of the second cycle of the reference clock, and outputs a pulsetrain of a desired frequency.
 3. A variable-frequency pulse generatorwhich executes one cycle of output control of the pulse train by twocycles of a reference clock, comprising: an inversion unit which invertsa reference value regulated by the reference clock; a selection unitwhich selects the reference value after inversion, when an overflow hasoccurred, and in any other event selects a predetermined value whichchanges depending on a set speed; a data holding unit which latches anoutput of a previous stage, being the present value of a result ofaddition, in the second cycle of the reference clock and at apredetermined timing of an overflow prevention signal; an addition unitwhich adds the value selected by the selection unit and the data latchedby the data holding unit; a first comparison unit which compares thevalue obtained by the addition unit as a result of addition and thereference value; a judgment unit which judges whether a condition “theoverflow frequency is an even number” and “0≦addition result<referencevalue” is satisfied, or whether a condition “the overflow frequency isan even number” and “reference value≦addition result” is satisfied, orwhether conditions “the overflow frequency is an odd number” and“0<addition result≦reference value” are satisfied, or whether conditions“the overflow frequency is an odd number” and “reference value≦additionresult” are satisfied, and outputs a specified signal corresponding to aresult of the judgment; a pulse train output unit which latches thespecified signal at a predetermined timing of the second cycle of thereference clock, and outputs a pulse train of a desired frequency; asecond comparison unit which compares the data latched by the dataholding unit and the reference value, and when a condition “latcheddata≧reference value” is satisfied, judges that the overflow hasoccurred; and an overflow prevention unit which outputs the overflowprevention signal at a predetermined timing of the first cycle of thereference clock, when the second comparison unit has judged that theoverflow has occurred.
 4. A variable-frequency pulse generator whichexecutes one cycle of output control of the pulse train by two cycles ofa reference clock, comprising: an inversion unit which inverts a firstreference value regulated by the reference clock; a selection unit whichselects the first reference value after inversion, when an overflow hasoccurred, and in any other event selects a predetermined value whichchanges depending on a set speed; a data holding unit which latches anoutput of a previous stage, being the present value of a result ofaddition, in the second cycle of the reference clock and at apredetermined timing of the overflow prevention signal; an addition unitwhich adds the value selected by the selection unit and the data latchedby the data holding unit; a first comparison unit which compares thevalue obtained by the addition unit as a result of addition and thefirst reference value; a second comparison unit which compares the valueobtained by the addition unit as a result of addition and a secondreference value which is half of the first reference value; a judgmentunit which judges whether a condition “0≦addition result<secondreference value” is satisfied, or whether a condition “second referencevalue≦addition result<first reference value” is satisfied, or whether acondition “first reference value≦addition result<(second referencevalue×3)” is satisfied, or whether a condition “(second referencevalue×3)≦addition result” is satisfied, and outputs a specified signalcorresponding to a result of the judgment; a pulse train output unitwhich latches the specified signal at a predetermined timing of thesecond cycle of the reference clock, and outputs a pulse train of adesired frequency; a third comparison unit which compares the datalatched by the data holding unit and the first reference value, and whena condition “latched data>first reference value” is satisfied, judgesthat the overflow has occurred; and an overflow prevention unit whichoutputs the overflow prevention signal at a predetermined timing of thefirst cycle of the reference clock, when the third comparison unit hasjudged that the overflow has occurred.